1. Field of the Invention
The present invention is directed to integrated circuit design software used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to estimating delay together with crosstalk delay in an integrated circuit design.
2. Description of Related Art
In one previous approach to integrated circuit design, a crosstalk analysis is performed after placement and detailed routing. A timing closure step is then performed to detect timing violations in the design, and another placement and detailed routing is performed to resolve the timing violations. The crosstalk analysis is typically based on a transistor level simulation and is highly accurate. A disadvantage of this method is that several iterations may be required to resolve all timing violations. The most time consuming step is timing closure after parasitic analysis, that is, with crosstalk analysis.